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ADS-930
16-Bit, 500kHz Sampling A/D Converters
INNOVATION and EXCELLENCE
FEATURES
* * * * * * * * * 16-bit resolution 500kHz sampling rate Functionally complete Excellent dynamic performance 83dB SNR, -89dB THD No missing codes Small, 40-pin, TDIP package 3.5 Watts power dissipation On-board FIFO
PIN
INPUT/OUTPUT CONNECTIONS
FUNCTION +10V REF. OUT BIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST +15V SUPPLY COMP. BITS ENABLE FIFO READ ANALOG GROUND -15V SUPPLY ANALOG GROUND OVERFLOW EOC +5V SUPPLY START CONVERT DIGITAL GROUND FSTAT1 FSTAT2 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 ANALOG GROUND BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 DIGITAL GROUND FIFO/DIR BIT 15 BIT 16 (LSB)
GENERAL DESCRIPTION
The low-cost ADS-930 is a high-performance, 16-bit, 500kHz sampling A/D converter. This device accurately samples fullscale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-930 is optimized to achieve a THD of -89dB and an SNR of 83dB. Packaged in a small, 40-pin, ceramic TDIP, the functionally complete ADS-930 contains a fast-settling sample-hold amplifier, a subranging (three-pass) A/D converter, an internal reference, an on-board FIFO, timing and control logic, threestate outputs and error-correction circuitry. Digital inputs/ outputs are TTL. Requiring 15V and +5V supplies, the ADS-930 typically dissipates 3.5 Watts. The unit is offered with a bipolar input range of 5V or a unipolar input range of 0 to -10V. Models are available for use in either commercial (0 to +70C) or military (-55 to +125C) operating temperature ranges. Typical applications include radar, sonar, medical/graphic imaging, and FFT spectrum analysis.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
19 FSTAT1 20 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 23 FIFO/DIR 10 FIFO READ 40 BIT 1 (MSB) 39 BIT 1 (MSB) +10V REF. OUT 1 POWER AND GROUNDING +5V SUPPLY +15V SUPPLY -15V SUPPLY ANALOG GROUND DIGITAL GROUND 16 7 12 4, 11, 13, 30 18, 24 BIPOLAR 2 OFFSET ADJUST 5 3-PASS ANALOG-TO-DIGITAL CONVERTER PRECISION +10V REFERENCE 38 BIT 2 37 BIT 3 36 BIT 4 CUSTOM GATE ARRAY 3-STATE OUTPUT REGISTER 35 BIT 5 34 BIT 6 33 BIT 7 32 BIT 8 31 BIT 9 29 BIT 10 28 BIT 11 27 BIT 12 26 BIT 13 25 BIT 14 22 BIT 15 21 BIT 16 (LSB) 9 ENABLE 14 OVERFLOW
OFFSET ADJUST CKT.
ANALOG INPUT 3
S/H
START CONVERT 17 EOC 15 COMP. BITS 8
TIMING AND CONTROL LOGIC
Figure 1. ADS-930 Functional Block Diagram
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048 (U.S.A.) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * Email: datellit@mcimail.com
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ABSOLUTE MAXIMUM RATINGS
PARAMETERS +15V Supply (Pin 7) -15V Supply (Pin 12) +5V Supply (Pin 16) Digital Inputs (Pin 8, 9, 10, 17, 23) Analog Input (Pin 3) Unipolar Bipolar Lead Temperature (10 seconds) LIMITS 0 to +16 0 to -16 0 to +6 -0.3 to +VDD +0.3 -12.5 to +12.5 -7.5 to +12.5 +300 UNITS Volts Volts Volts Volts Volts Volts C
PHYSICAL/ENVIRONMENTAL
PARAMETERS Operating Temp. Range, Case ADS-930MC ADS-930MM Thermal Impedance jc ca Storage Temperature Range Package Type Weight MIN. 0 -55 -- -- -65 TYP. -- -- MAX. +70 +125 UNITS C C
4 -- C/Watt 18 -- C/Watt -- +150 C 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams)
FUNCTIONAL SPECIFICATIONS
(TA = +25C, VCC = 15V, +VDD = +5V, 500kHz sampling rate, and a minimum 5 minute warmup unless otherwise specified.) +25C ANALOG INPUTS Input Voltage Range Bipolar Unipolar Input Resistance Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Unipolar Zero Error (Tech Note 2) Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (-0.5dB) dc to 100kHz 100kHz to 250kHz Total Harmonic Distortion (-0.5dB) dc to 100kHz 100kHz to 250kHz Signal-to-Noise Ratio (w/o distortion, -0.5dB) dc to 100kHz 100kHz to 250kHz Signal-to-Noise Ratio (& distortion, -0.5dB) dc to 100kHz 100kHz to 250kHz Two-Tone Intermodulation Distortion (fin = 100kHz, 240kHz, fs = 500kHz, -0.5dB) Noise Input Bandwidth (-3dB) Small Signal (-20dB input) Large Signal (-0.5dB input) Feedthrough Rejection (fin = 250kHz) Slew Rate -- -- -- -- 81 -- 78 -- -- -- -- -- -- -- -91 -86 -89 -84 83 80 81 78 -82 150 2 1.1 92 80 -- -- -81 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 81 -- 77 -- -- -- -- -- -- -- -91 -86 -89 -84 83 80 81 78 -82 150 2 1.1 92 80 -- -- -81 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 75 -- 72 -- -- -- -- -- -- -- -87 -84 -85 -82 80 79 78 76 -81 150 2 1.1 92 80 -- -- -76 -- -- -- -- -- -- -- -- -- -- -- dB dB dB dB dB dB dB dB dB Vrms MHz MHz dB V/s -- -- -- -- -- -- -- -- 16 16 1.0 0.75 0.05 0.05 0.05 0.05 0.1 -- -- -- -- 0.18 0.085 0.085 0.15 0.15 -- -- -- -- -- -- -- -- -- 16 16 1.5 1.0 0.2 0.1 0.15 0.1 0.15 -- -- -- -- 0.5 0.25 0.25 0.25 0.35 -- -- -- -- -- -- -- -- -- 15 16 2.0 1.5 0.5 0.25 0.25 0.25 0.25 -- -- -- -- 0.8 0.5 0.5 0.5 0.65 -- Bits LSB LSB %FSR %FSR %FSR %FSR % Bits +2.0 -- -- -- 175 -- -- -- -- 200 -- +0.8 +20 -20 215 +2.0 -- -- -- 175 -- -- -- -- 200 -- +0.8 +20 -20 215 +2.0 -- -- -- 175 -- -- -- -- 200 -- +0.8 +20 -20 215 Volts Volts A A ns MIN. -- -- 1.4 -- TYP. 5 0 to -10 1.5 7 MAX. -- -- 1.7 15 MIN. -- -- 1.4 -- 0 to +70C TYP. 5 0 to -10 1.5 7 MAX. -- -- 1.7 15 MIN. -- -- 1.4 -- -55 to +125C TYP. 5 0 to -10 1.5 7 MAX. -- -- 1.7 15 UNITS Volts Volts k pF
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+25C DYNAMIC PERFORMANCE (Cont.) Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to 0.003%FSR, 10V step) Overvoltage Recovery Time A/D Conversion Rate ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Falling Edge of ENABLE to Output Data Valid Output Coding POWER REQUIREMENTS Power Supply Ranges +15V Supply -15V Supply +5V Supply Power Supply Currents +15V Supply -15V Supply +5V Supply Power Dissipation Power Supply Rejection +14.5 -14.5 +4.75 -- -- -- -- -- +15.0 -15.0 +5.0 +110 -100 +80 3.5 -- +15.5 -15.5 +5.25 +130 -125 +90 4.25 0.02 +14.5 -14.5 +4.75 -- -- -- -- -- +15.0 -15.0 +5.0 +110 -100 +80 3.5 -- +15.5 -15.5 +5.25 +130 -125 +90 4.25 0.02 +14.5 -14.5 +4.75 -- -- -- -- -- +15.0 -15.0 +5.0 +110 -100 +80 3.5 -- +15.5 -15.5 +5.75 +130 -125 +90 4.25 0.02 Volts Volts Volts mA mA mA Watts %FSR/%V +2.4 -- -- -- -- -- -- -- -- -- +0.4 -4 +4 +2.4 -- -- -- -- -- -- -- -- +0.4 -4 +4 +2.4 -- -- -- -- -- -- -- -- +0.4 -4 +4 Volts Volts mA mA ns +9.95 -- -- +10.0 10 -- +10.05 -- 1 +9.95 -- -- +10.0 10 -- +10.05 -- 1 +9.95 -- -- +10.0 10 -- +10.05 -- 1 Volts ppm/C mA MIN. -- -- -- -- 500 TYP. 10 5 460 600 -- MAX. -- -- 545 1000 -- MIN. -- -- -- -- 500 0 to +70C TYP. 10 5 460 600 -- MAX. -- -- 545 1000 -- MIN. -- -- -- -- 500 -55 to +125C TYP. 10 5 460 600 -- MAX. -- -- 545 1000 -- UNITS ns ps rms ns ns kHz
-- 10 -- -- 10 -- -- 10 Complementary Offset Binary; Complementary Two's Complement, Offset Binary, Two's Complement
Footnotes:
All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. The device must be continuously converting during this time. When COMP. BITS (pin 8) is low, logic loading "0" will be -350A. A 200ns wide start convert pulse is used for all production testing. For
6.02
applications requiring less than a 500kHz sampling rate, wider start convert pulses can be used. Effective bits is equal to:
(SNR + Distortion) - 1.76 + 20 log Full Scale Amplitude Actual Input Amplitude
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-930 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 11, 13, 18, 24 and 30) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +10V reference output to ground with 4.7F tantalum capacitors in parallel with 0.1F ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-930 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 8 (COMP. BITS) is used to select the digital output coding format of the ADS-930. See Tables 3a and 3b. When this pin has a TTL logic "0" applied, it complements all of the ADS-930's digital outputs. When pin 8 has a logic "1" applied and the ADS-930 is operated within its unipolar (0 to -10V) input range, the output coding is straight binary. Applying a logic "0" to pin 8 under these conditions changes the output coding to complementary binary. When pin 8 has a logic "1" applied and the ADS-930 is operated within its bipolar (5V) input range, the output coding is offset binary. Applying a logic "0" to pin 8 under these conditions changes the coding to complementary offset binary. Using the MSB output (pin 40) instead of the MSB output (pin 39) under these conditions changes the respective output codings to two's complement and complementary two's complement. Pin 8 is TTL-compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 8 allowing
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TECHNICAL NOTES cont. it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect ENABLE (pin 9) to a logic "0" (low). To disable, connect pin 9 to a logic "1" (high). 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the falling edge of START CONVERT to the falling edge of EOC). FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 9), data from the first conversion will appear at the output of the ADS-930. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both = "1"), it can be read by dropping the FIFO READ line (pin 10) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. If a read command is issued after the FIFO has been emptied, the last word (the 16th conversion) will remain present at the outputs. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-930 into its "direct" mode (logic "0" applied to pin 23, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 10). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs will change 40ns after the control signals have been applied. FIFO Status, FSTAT1 and FSTAT2 The status of the data in the FIFO can be monitored by reading the two status pins, FSTAT1 (pin 19) and FSTAT2 (pin 20). CONTENTS Empty (0 words) INTERNAL FIFO OPERATION
The ADS-930 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and OVERFLOW bits. Pins 23 (FIFO/DIR) and 10 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 19 (FSTAT1) and 20 (FSTAT2). When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 23 has a logic "0" applied, the FIFO is transparent, and the output data goes directly to the output three-state register (whose operation is controlled by pin 9 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-930 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-930's operation. FIFO WRITE and READ Modes Once the FIFO has been enabled (pin 23 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 10). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 10 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the
Table 1. FIFO Delays DELAY Direct mode to FIFO enabled FIFO enabled to direct mode FIFO READ to output data valid FIFO READ to status update when changing from 0 0 1 1 1
0 0 0
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CALIBRATION PROCEDURE
(Refer to Figure 2 and Tables 3a, and 3b) Connect the converter per Table 2 for the appropriate input voltage range. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-930's initial accuracy errors and may not be able to compensate for additional system errors. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-930, offset adjusting is normally accomplished when the analog input is 0 minus 1/2 LSB (-76V). See Table 3b for the proper bipolar and unipolar output coding. Gain adjusting is accomplished when the analog input is at nominal full scale minus 11/2 LSB's (-9.999771V for unipolar and +4.999771V for bipolar). Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. Zero/Offset Adjust Procedure 1. Apply a train of pulses to the START CONVERT input (pin 17) so that the converter is continuously converting. 2. For unipolar or bipolar zero/offset adjust, apply -76.3V to the ANALOG INPUT (pin 3). 3. For a bipolar input - adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 8 tied high (offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 8 tied low (complementary offset binary). For a unipolar input - adjust the offset potentiometer until all output bits are 0's and the LSB flickers between 0 and 1 with pin 8 tied high (straight binary) or until all output bits are 1's and the LSB flickers between 0 and 1 with pin 8 tied low (complementary binary). 4. Two's complement coding requires using BIT 1 (MSB) (pin 40). With pin 8 tied high, adjust the trimpot until the output code flickers between all 0's and all 1's. INPUT RANGE
0 to -10V 5V Table 2. Input Connections
+15V 20k -15V +15V 20k -15V
6 GAIN ADJUST +5V 4.7F 0.1F DIGITAL 18, 24 GROUND +5V 16 DIGITAL
5 OFFSET ADJUST
+
+15V 4.7F 4.7F -15V
7 +15V 0.1F 4, 11 ANALOG 13, 30 GROUND 0.1F 12 -15V
ADS-930
9 ENABLE 23 FIFO/DIR 19 FSTAT1 ANALOG INPUT 20 FSTAT2 FIFO READ 10 2 BIPOLAR 1 +10V REF. OUT 0.1F 4.7F START CONVERT 17 COMP. BITS 8 3
15 14 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 22 21
EOC OVERFLOW BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB)
+
+5V
Figure 2. Bipolar Connection Diagram
INPUT PIN
Pin 3 Pin 3
TIE TOGETHER
Pins 2 and 4 Pins 1 and 2
Table 3a. Setting Output Coding Selection (Pin 8)
OUTPUT FORMAT
Straight Binary Complementary Binary Complementary Offset Binary Offset Binary Complementary Two's Complement (Using MSB, pin 40) Two's Complement (Using MSB, pin 40)
PIN 8 LOGIC LEVEL
1 0 0 1 0 1
Table 3b. Output Coding
STRAIGHT BIN UNIPOLAR SCALE -FS +1 LSB -FS +1 1/2 LSB -7/8 FS -3/4 FS -1/2FS -1/2FS -1/2LSB -1/4FS -1/8FS -1 LSB -1/2LSB 0 INPUT RANGE 0 to -10V -9.999847 -9.999771 -8.750000 -7.500000 -5.000000 -4.999924 -2.500000 -1.250000 -0.000153 -0.000076 0.000000 COMP. BINARY OUTPUT CODING MSB 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 1100 0000 0000 1000 0000 0000 0111 1111 1111 0100 0000 0000 0010 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 0000 LSB 1111 0000 0000 0000 1111 0000 0000 0001 0000 MSB LSB MSB LSB MSB 1000 0000 0000 LSB "0" to "1" 1001 1111 1111 1011 1111 1111 1111 1111 1111 0000 0000 0000 0011 1111 1111 0101 1111 1111 0111 1111 1111 LSB "1" to "0" TWO'S COMP. LSB 0000 1111 1111 1111 0000 1111 1111 1110 INPUT RANGE 5V +4.999847 +4.999771 +3.750000 +2.500000 0.000000 -0.000076 -2.500000 -3.750000 -4.999847 -4.999924 -5.000000 BIPOLAR SCALE +FS -1 LSB +FS -1 1/2 LSB +3/4 FS +1/2 FS 0 -1/2 LSB -1/2 FS -3/4 FS -FS +1 LSB -FS + 1/2 LSB -FS
0000 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 0000 0000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 LSB "1" to "0" 1111 1111 1111 1111 OFFSET BINARY
0111 1111 1111 1111 LSB "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 LSB "0" to "1" 1000 0000 0000 0000 COMP. TWO'S COMP.
01111111 1111 1111
COMP. OFF. BIN.
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Gain Adjust Procedure 1. Apply +4.999771V to the ANALOG INPUT (pin 3) for bipolar gain adjust or apply -9.999771V to pin 3 for unipolar gain adjust. 2. For a unipolar input - adjust the gain potentiometer until all output bits are 1's and the LSB flickers between a 1 and 0 with pin 8 tied high (straight binary) or until all output bits are 0's and the LSB flickers between a 1 and 0 with pin 8 tied low (complementary binary). For a bipolar input - adjust the gain potentiometer until all output bits are 1's and the LSB flickers between a 1 and 0 with pin 8 tied low (complementary offset binary) or until all output bits are 0's and the LSB flickers between a 1 and 0 with pin 8 tied high (offset binary). 3. Two's complement coding requires using pin 40. With pin 8 tied high, adjust the gain trimpot until the output code flickers equally between 1000 0000 0000 0000 and 1000 0000 0000 0001. specified over operating temperature (case) ranges of 0 to +70C and -55 to +125C. All room-temperature (TA = +25C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electricallyinsulating, thermally-conductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional data.
N+1
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and
N START CONVERT 175ns min., 200ns typ., 215ns max .
10ns min., 25ns max. Acquisition Time INTERNAL S/H Hold 1.54s typ. 460ns typ. 545ns max. 140ns max. EOC 780ns 30ns Conversion Time 700ns 30ns
10ns min. 25ns max.
1.39s min. OUTPUT DATA Data N-1 Valid Data N Valid 30ns min . Note: Scale is approximately 50ns per division. Invalid Data
Figure 3. ADS-930 Timing Diagram
Figure 4. FFT Analysis of ADS-930
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+5V C12 0.1MF 2 20 1
P3
ANALOG INPUT +5V SG2 C10 0.1MF 2 74HCT373 20 1Q 2Q 3Q 4Q U2 5Q 6Q 7Q 8Q ENBL LTCH 10 P1 +5V C11 0.1MF 2 74HCT373 3 1D 29 28 27 26 B13 B14 DGND DIR DGND FS1 20 2 FS2 B15 B16 25 24 23 22 21 J13 J15 J14 4 2D 7 3D 8 4D 13 5D 14 6D 17 7D 18 8D 11 LTCH ENBL 10 8Q 1 TRIG 2 J16 J17 1 J18 7Q 19 B16 4 (LSB) 3 6Q 16 B15 6 5 U3 5Q 15 B14 8 7 4Q 12 B13 10 9 3Q 9 B12 12 B12 11 2Q 6 B11 14 13 1Q 5 B10 16 15 20 2 B9 18 17 1 P1 15 16 19 1 12 9 6 B3 30 B4 28 B5 26 B6 24 B7 22 B8 20 19 21 23 25 27 29 5 B2 32 31 2 B1 34 (MSB) 33 3 1D 2D 3D 4D 5D 6D 7D 8D 4 7 8 1 REF ADS-930 13 2 B.P. B1 14 3 ANAIN B2 17 4 AGND 18 3 11 2 GAIN B5 B6 B7 B8 B9 AGND B10 B11 30 31 32 33 34 +15V COMPB ENB READ U1 AGND -15V AGND O.F. EOC +5V TRIG C8 1 J4 33PF J6 9 10 11 12 13 14 15 -15V +5V 17 5 U5 4 74HCT86 +15V 7 3 U5 1 14 74HCT86 C4 2.2MF 19 18 C2 L1 16 2MH J9 P1-9 J12 P1-7 +5V -15V +5V J11 J5 J7 J8 J10 P1-11 -15V 8 7 0.22MF +15V 6 35 R4 15K C13 R2 20K GAIN 5 OFFSET B4 36 B3 37 2 1 PULSE WIDTH R3 20K +15V 3 38 39 B1 40 1
1
2 +15V
R1 20K C7 .22MF C14 0.1MF 2 10 C15 2.2MF 1
3 ENBL
(SEE NOTE 1)
74HCT373 3 1D 4 2D 7 3D 8 4D 13 5D U4 14 6D 17 7D 18 8D 11 LTCH 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2 5 6 9 12 15 16 19 1 B1 O.F. EOC
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OFFSET
-15V J3 +5V J2 J1
11
U5
12 13
74HCT86
+5V
P4
16
TRIGGER
1
2
8 7 6 5 4 3 2
U6 74HCT 123
9 10 11 12 13 14 15
1
SG1
P2
2
1
4 2.2MF
3
C5
C6 2+
+
7
6 C9 SG3 1 0.1MF 2 +5V NOTES: 1. C14 & C15 SHOULD BE 16V OR GREATER. 2. SG1-SG3 ARE INITIALLY OPEN. 10 +5V U5 9 74HCT86 8
ENABLE COMPB ENB READ DIR FS1 FS2
6
5
0.1MF 1
U1-8 U1-9 U1-10
8
7
10
9
12
11
C1
2
14
13
+ 0.1MF 1 2.2MF
16
15
18
17
20
19
C3
2+
22
21
.1MF
1
24
23
26
25
ADS-930
Figure 5. ADS-930 Evaluation Board Schematic.
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MECHANICAL DIMENSIONS INCHES (mm)
2.12/2.07 (53.85/52.58)
40
21
Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) 0.010 (0.254) 3 place decimal (.XXX) 0.005 (0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating
1.11/1.08 (28.20/27.43)
1
20
0.100 TYP. (2.540) 1.900 0.008 (48.260) 0.245 MAX. (6.223)
PIN 1 INDEX ( ON TOP)
0.200/0.175 (5.080/4.445)
0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 0.002 (0.457) 0.045/0.035 (1.143/0.889) 0.110/0.090 (2.794/2.286) SEATING PLANE 0.035/0.015 (0.889/0.381) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286
ORDERING INFORMATION
OPERATING TEMP. RANGE 0 to +70C -55 to +125C ANALOG INPUT 0 to -10V, 5V 0 to -10V, 5V
MODEL NUMBER ADS-930MC ADS-930MM
ACCESSORIES ADS-EVAL3 HS-40 Evaluation Board (without ADS-930) Heat Sink for all ADS-930 models
Receptacles for pc board mounting can be ordered through AMP, Inc., part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.
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R E G I S T E R E D
IN N O V A T I O N a n d E X C E L L E N C E
DS-0307PB
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DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Email: datellit@mcimail.com Data Sheet Fax Back: (508) 261-2857
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

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